This invention relates to an instruction decode unit of computers and more particularly to instruction decode method and arrangement suitable for a decoder of high-speed microprocessors.
Conventionally, in this type of arrangement, data sent from an instruction register is supplied to a single instruction decoder and decoded thereby, as disclosed in JP-B-62-11734 based on U.S. patent application Ser. No. 6174 filed Jul. 30, 1979.
Generally, when the machine cycle or the fundamental unit of operation of the microprocessor is reduced, noise is generated and power consumption is increased. The prior art arrangement does not however take into account the desirability of preventing the noise and reducing the power consumption, and so high-speed operation is difficult to achieve in such an arrangement.
For example, in order to ensure high-speed operation of a processor having an instruction decoder formed of a programmable logic array (PLA), the PLA must be a dynamic NOR-NOR type PLA.
This type of PLA has two planes of NOR logic arrays connected in series and the NOR logic array having word wires which are identical in number to the outputs and which are charged in advance is operated by drawing out electric charges from all word wires which do not meet a specified condition.
In charging and discharging the word wires, a potential drop in the power supply is caused by an instantaneous current flow and the thus caused potential drop increase in proportion to the operation speed to generate noises affecting other logic components. In addition, the amount of electric charges which are moved during charge/discharge of the word wires leads to a power consumption which also increases in proportion to the operation speed.
U.S. Pat. No. 4,160,289 proposes a microprogram control unit in which the output circuit of a microinstruction memory incorporates a primary decoder and a secondary decoder and the latter is activated in response to a switching command produced from the former. This proposal simply employs two stages of decoders for decoding instructions, especially, microinstructions and has no improvement over the first-mentioned prior art arrangement with respect to prevention of noise and reduction of power consumption.